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general description the max5873 is an advanced 12-bit, 200msps, dual digital-to-analog converter (dac). this dac meets the demanding performance requirements of signal synthesis applications found in wireless base stations and other communications applications. operating from 3.3v and 1.8v supplies, this dual dac offers exceptional dynamic performance such as 78dbc spurious-free dynamic range (sfdr) at f out = 16mhz and supports update rates of 200msps, with a power dissipation of only 255mw. the max5873 utilizes a current-steering architecture that supports a 2ma to 20ma full-scale output current range, and allows a 0.1v p-p to 1v p-p differential output voltage swing. the max5873 features an integrated 1.2v bandgap reference and control amplifier to ensure high-accuracy and low-noise performance. a separate reference input (refio) allows for the use of an exter- nal reference source for optimum flexibility and improved gain accuracy. the digital and clock inputs of the max5873 accept 3.3v cmos voltage levels. the max5873 features a flexible input data bus that allows for dual-port input or a single-interleaved data port. the max5873 is avail- able in a 68-pin qfn package with an exposed paddle (ep) and is specified for the extended temperature range (-40? to +85?). refer to the max5874 and max5875 data sheets for pin-compatible 14-bit and 16-bit versions of the max5873, respectively. refer to the max5876 for an lvds-compatible version of the max5873. applications base stations: single-carrier umts, cdma, gsm communications: fixed broadband wireless access, point-to-point microwave direct digital synthesis (dds) cable modem termination system (cmts) automated test equipment (ate) instrumentation features ? 200msps output update rate ? noise spectral density = -152dbfs/hz at f out = 16mhz ? excellent sfdr and imd performance sfdr = 78dbc at f out = 16mhz (to nyquist) sfdr = 73dbc at f out = 80mhz (to nyquist) imd = -85dbc at f out = 10mhz imd = -74dbc at f out = 80mhz ? aclr = 74db at f out = 61mhz ? 2ma to 20ma full-scale output current ? cmos-compatible digital and clock inputs ? on-chip 1.2v bandgap reference ? low 255mw power dissipation ? 68-lead qfn-ep package ? evaluation kit available (max5873evkit) max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs ________________________________________________________________ maxim integrated products 1 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 dv dd3.3 av dd1.8 a10 qfn top view a11 dv dd1.8 n.c. n.c. n.c. n.c. b0 b1 b2 52 53 b3 b4 dacref av dd3.3 gnd gnd av dd3.3 outqp outqn gnd gnd outip outin av dd3.3 gnd av dd3.3 b9 b10 b11 seliq gnd xor dori pd torb clkp 35 36 37 clkn gnd av clk gnd n.c. n.c. n.c. n.c. refio gnd av dd3.3 gnd gnd a0 a1 a2 a3 48 b8 a4 64 a9 65 66 67 a6 a7 a8 68 a5 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 gnd av dd1.8 34 33 49 50 b6 b7 51 b5 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 fsadj 17 max5873 pin configuration ordering information 19-3446; rev 3; 1/07 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad. + denotes lead-free package. d = dry pack. evaluation kit available part temp range pin- package pkg code max5873egk-d -40? to +85? 68 qfn-ep* g6800-4 max5873egk+d -40? to +85? 68 qfn-ep* g6800-4 selector guide part resolution (bits) update rate (msps) logic inputs max5873 12 200 cmos max5874 14 200 cmos max5875 16 200 cmos max5876 12 250 lvds max5877 14 250 lvds max5878 16 250 lvds
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd1.8 , dv dd1.8 to gnd, dacref ................. -0.3v to +2.16v av dd3.3 , dv dd3.3 , av clk to gnd, dacref ....... -0.3v to +3.9v refio, fsadj to gnd, dacref ........-0.3v to (av dd3.3 + 0.3v) outip, outin, outqp, outqn to gnd, dacref .................................-1v to (av dd3.3 + 0.3v) clkp, clkn to gnd, dacref..............-0.3v to (av clk + 0.3v) a11/b11?0/b0, xor, seliq to gnd, dacref ...................................-0.3v to (dv dd3.3 + 0.3v) torb, dori , pd to gnd, dacref........-0.3v to (dv dd3.3 + 0.3 continuous power dissipation (t a = +70?) 68-pin qfn-ep (derate 41.7mw/? above +70?) (note 1) ...........3333.3mw thermal resistance ja (note 1)...................................+24?/w operating temperature range ......................... -40? to +85? junction temperature .................................................... +150? storage temperature range ........................... -60? to +150? lead temperature (soldering, 10s) ............................... +300? parameter symbol conditions min typ max units static performance resolution 12 bits integral nonlinearity inl measured differentially 0.2 lsb differential nonlinearity dnl measured differentially ?.13 lsb offset error os -0.025 0.001 +0.025 %fs offset-drift tempco 10 ppm/ c full-scale gain error ge fs external reference 1%fs internal reference 100 gain-drift tempco external reference 50 ppm/ c full-scale output current i out (note 3) 2 20 ma output compliance single-ended -0.5 +1.1 v output resistance r out 1m ? output capacitance c out 5pf dynamic performance clock frequency f clk 1 200 mhz f dac = f clk / 2, single-port mode 1 100 output update rate f dac f dac = f clk , dual-port mode 1 200 msps f dac = 150mhz f out = 16mhz, -12dbfs -152 noise spectral density f dac = 200mhz f out = 80mhz, -12dbfs -153 dbfs/ hz electrical characteristics (av dd3.3 = dv dd3.3 = av clk = 3.3v, av dd1.8 = dv dd1.8 = 1.8v, gnd = 0, f clk = f dac , external reference v refio = 1.25v, output load 50 ? double terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) note 1: themal resistors based on a multilayer board with 4 x 4 via array in exposed paddle area.
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs _______________________________________________________________________________________ 3 electrical characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = 3.3v, av dd1.8 = dv dd1.8 = 1.8v, gnd = 0, f clk = f dac , external reference v refio = 1.25v, output load 50 ? double terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units f out = 1mhz, 0dbfs 86 f out = 1mhz, -6dbfs 82 f out = 1mhz, -12dbfs 80 f out = 10mhz, -12dbfs 85 f dac = 100mhz f out = 30mhz, -12dbfs 80 f out = 10mhz, -12dbfs 80 f out = 16mhz, -12dbfs, t a +25 o c 72 78 f out = 16mhz, -12dbfs 68 78 f out = 50mhz, -12dbfs 77 spurious-free dynamic range to nyquist sfdr f dac = 200mhz f out = 80mhz, -12dbfs 73 dbc spurious-free dynamic range, 25mhz bandwidth sfdr f dac = 150mhz f out = 16mhz, -12dbfs 85 dbc f dac = 100mhz f out1 = 9mhz, -7dbfs; f out2 = 10mhz, -7dbfs -85 two-tone imd ttimd f dac = 200mhz f out1 = 79mhz, -7dbfs; f out2 = 80mhz, -7dbfs -74 dbc four-tone imd, 1mhz frequency spacing, gsm model ftimd f dac = 150mhz f out = 16mhz, -12dbfs -82 dbc adjacent channel leakage power ratio 3.84mhz bandwidth, w-cdma model aclr f dac = 184.32mhz f out = 61.44mhz 74 db output bandwidth bw -1db (note 4) 240 mhz inter-dac characteristics f out = dc - 80mhz 0.2 gain matching ? gain f out = dc +0.01 db gain-matching tempco ? gain/ c 20 ppm/ c phase matching ? phase f out = 60mhz 0.25 d egr ees phase-matching tempco ? phase/ c 0.002 d eg r ees/ c channel-to-channel crosstalk f clk = 200mhz, f out = 50mhz, 0dbfs -70 db reference internal reference voltage range v refio 1.14 1.2 1.26 v reference input compliance range v refiocr 0.125 1.250 v reference input resistance r refio 10 k ? reference voltage drift tco ref 25 ppm/ c
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs 4 _______________________________________________________________________________________ electrical characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = 3.3v, av dd1.8 = dv dd1.8 = 1.8v, gnd = 0, f clk = f dac , external reference v refio = 1.25v, output load 50 ? double terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) parameter symbol conditions min typ max units analog output timing (see figure 4) output fall time t fall 90% to 10% (note 5) 0.7 ns output rise time t rise 10 % to 90% (note 5) 0.7 ns output-voltage settling time t settle output settles to 0.025% fs (note 5) 14 ns output propagation delay t pd excluding data latency (note 5) 1.1 ns glitch impulse measured differentially 1 pv s i outfs = 2ma 30 output noise n out i outfs = 20ma 30 pa/ hz timing characteristics data to clock setup time t setup referenced to rising edge of clock (note 6) -0.6 -1.2 ns data to clock hold time t hold referenced to rising edge of clock (note 6) 2.1 1.5 ns latency to i output 9 single-port (interleaved mode) data latency latency to q output 8 clock cycles dual-port (parallel mode) data latency 5.5 clock cycles minimum clock pulse-width high t ch clkp, clkn 2.4 ns minimum clock pulse-width low t cl clkp, clkn 2.4 ns cmos logic inputs (a11/b11?0/b0, xor, seliq, pd, torb, dori ) input logic high v ih 0.7 x dv dd3.3 v input logic low v il 0.3 x dv dd3.3 v input leakage current i in 120a pd, torb, dori internal pulldown resistance v pd = v torb = v dori = 3.3v 1.5 m ? input capacitance c in 2.5 pf clock inputs (clkp, clkn) sine wave > 1.5 differential input voltage swing square wave > 0.5 v p-p differential input slew rate sr clk (note 7) > 100 v/? external common-mode voltage range v com av clk / 2 0.3 v input resistance r clk 5k ? input capacitance c clk 2.5 pf power supplies av dd3.3 3.135 3.3 3.465 analog supply voltage range av dd1.8 1.710 1.8 1.890 v
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs _______________________________________________________________________________________ 5 electrical characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = 3.3v, av dd1.8 = dv dd1.8 = 1.8v, gnd = 0, f clk = f dac , external reference v refio = 1.25v, output load 50 ? double terminated, transformer-coupled output, i outfs = 20ma, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 2) note 2: specifications at t a +25? are guaranteed by production testing. specifications at t a < +25? are guaranteed by design and characterization data. note 3: nominal full-scale current i outfs = 32 x i ref . note 4: this parameter does not include update-rate-dependent effects of sin(x)/x filtering inherent in the max5873. note 5: parameter measured single-ended into a 50 ? termination resistor. note 6: not production tested. guaranteed by design and characterization data. note 7: a differential clock input slew rate of > 100v/? is required to achieve the specified dynamic performance. note 8: parameter defined as the change in midscale output caused by a ?% variation in the nominal supply voltage. typical operating characteristics (av dd3.3 = dv dd3.3 = av clk = 3.3v, av dd1.8 = dv dd1.8 = 1.8v, external reference, v refio = 1.25v, r l = 50 ? double-terminated, i outfs = 20ma, t a = +25?, unless otherwise noted.) single-tone sfdr vs. output frequency (f clk = 50msps) max5873 toc01 f out (mhz) sfdr (dbc) 20 15 10 5 20 40 60 80 100 0 025 -12dbfs -6dbfs 0dbfs single-tone sfdr vs. output frequency (f clk = 100msps) max5873 toc02 f out (mhz) sfdr (dbc) 40 30 20 10 20 40 60 80 100 0 050 -12dbfs -6dbfs 0dbfs single-tone sfdr vs. output frequency (f clk = 150msps) max5873 toc03 f out (mhz) sfdr (dbc) 60 45 30 15 20 40 60 80 100 0 075 -12dbfs -6dbfs 0dbfs parameter symbol conditions min typ max units dv dd3.3 3.135 3.3 3.465 digital supply voltage range dv dd1.8 1.710 1.8 1.890 v clock supply voltage range av clk 3.135 3.3 3.465 v f dac = 200msps, f out = 1mhz 52 58 i avdd3.3 + i avclk power-down 0.001 ma f dac = 200msps, f out = 1mhz 24 32 analog supply current i avdd1.8 power-down 0.001 ma f dac = 200msps, f out = 1mhz 0.5 3 i dvdd3.3 power-down 0.001 ma f dac = 200msps, f out = 1mhz 20 25 digital supply current i dvdd1.8 power-down 0.001 ma f dac = 200msps, f out = 1mhz 255 300 mw power dissipation p diss power-down 14 ? power-supply rejection ratio psrr av dd3.3 = av clk = dv dd3.3 = +3.3v 5% (notes 7, 8) -0.1 +0.1 %fs/v
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs 6 _______________________________________________________________________________________ typical operating characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = 3.3v, av dd1.8 = dv dd1.8 = 1.8v, external reference, v refio = 1.25v, r l = 50 ? double-terminated, i outfs = 20ma, t a = +25?, unless otherwise noted.) two-tone imd vs. output frequency (1mhz carrier spacing, f clk = 200msps) max5873 toc07 f out (mhz) two-tone imd (dbc) 70 60 50 40 30 20 10 -90 -80 -70 -60 -50 -40 -100 080 -6dbfs -12dbfs sfdr vs. full-scale output current (f clk = 200mhz) max5873 toc08 f out (mhz) sfdr (dbc) 80 60 40 20 20 40 60 80 100 0 0 100 a out = -6dbfs 10ma 5ma 20ma sfdr vs. temperature (f clk = 200mhz) max5873 toc09 f out (mhz) sfdr (dbc) 80 60 40 20 75 80 85 90 70 0 100 a out = -6dbfs t a = +85 c t a = +25 c t a = -40 c integral nonlinearity vs. digital input code max5873 toc10 digital input code inl (lsb) 3072 2048 1024 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.4 0 4096 differential nonlinearity vs. digital input code max5873 toc11 digital input code dnl (lsb) 3072 2048 1024 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.4 0 4096 single-tone sfdr vs. output frequency (f clk = 200msps) max5873 toc04 f out (mhz) sfdr (dbc) 80 60 40 20 20 40 60 80 100 0 0100 -12dbfs -6dbfs 0dbfs two-tone imd vs. output frequency (1mhz carrier spacing, f clk = 100msps) max5873 toc05 f out (mhz) two-tone imd (dbc) 35 30 25 20 15 10 -90 -80 -70 -60 -50 -40 -100 540 -6dbfs -12dbfs two-tone imd (f clk = 100msps) max5873 toc06 f out (mhz) output power (dbfs) 34 32 30 28 26 -80 -60 -40 -20 0 -100 24 36 bw = 12mhz 2 x f out 1 - f out 2 2 x f out 2 - f out 1 f out1 f out1 = 29.9795mhz f out2 = 31.0049mhz f out2
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs _______________________________________________________________________________________ 7 power dissipation vs. clock frequency (f out = 10mhz) max5873 toc12 f clk (mhz) power dissipation (mw) 190 170 150 130 110 90 70 50 200 220 240 260 280 180 30 a out = 0dbfs typical operating characteristics (continued) (av dd3.3 = dv dd3.3 = av clk = 3.3v, av dd1.8 = dv dd1.8 = 1.8v, external reference, v refio = 1.25v, r l = 50 ? double-terminated, i outfs = 20ma, t a = +25?, unless otherwise noted.) power dissipation vs. supply voltage (f clk = 100mhz, f out = 10mhz) max5873 toc13 supply voltage (v) power dissipation (mw) 3.435 3.335 3.235 210 220 230 240 250 200 3.135 a out = 0dbfs external reference internal reference four-tone power ratio plot (f clk = 150mhz, f center = 31.6040mhz) max5873 toc14 f out (mhz) output power (dbfs) 36 34 32 30 28 -80 -60 -40 -20 0 -100 26 38 bw = 12mhz f out1 f out2 f out3 f out4 f out1 = 29.6997mhz f out3 = 32.4829mhz f out2 = 30.7251mhz f out4 = 34.0210mhz aclr for wcdma modulation, two carriers max5873 toc15 3.05mhz/div analog output power (dbm) -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -120 f clk = 184.32mhz f center = 30.72mhz aclr = 71.20db aclr for wcdma modulation, single carrier max5873 toc16 9.2mhz/div analog output power (dbm) -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 dc 92.16mhz f center = 30.72mhz f clk = 184.32mhz aclr = 76db wcdma baseband aclr max5873 toc17 number of carriers aclr (db) 4 3 2 1 65 70 75 80 85 60 alternate adjacent 76.9 79.0 76.8 78.3 76.7 77.6 75.7 76.4
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs 8 _______________________________________________________________________________________ 8 _______________________________________________________________________________________ pin description pin name function 1? a4, a3, a2, a1, a0 data bits a4?0. in dual-port mode, data is directed to the q-dac. in single-port mode, data bits are not used. connect bits a4?0 to gnd in single-port mode. 6?, 57?0 n.c. no connection. leave floating or connect to gnd. 10, 12, 13, 15, 20, 23, 26, 27, 30, 33, 36, 43 gnd converter ground 11 dv dd3.3 digital supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass with a 0.1? capacitor to gnd. 14, 21, 22, 31, 32 av dd3.3 analog supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass each pin with a 0.1? capacitor to gnd. 16 refio reference i/o. output of the internal 1.2v precision bandgap reference. bypass with a 1? capacitor to gnd. refio can be driven with an external reference source. see table 1. 17 fsadj full-scale adjust input. this input sets the full-scale output current of the dac. for a 20ma full- scale output current, connect a 2k ? resistor between fsadj and dacref. see table 1. 18 dacref current-set resistor return path. for a 20ma full-scale output current, connect a 2k ? resistor between fsadj and dacref. internally connected to gnd. do not use as a ground connection. 19, 34 av dd1.8 analog supply voltage. accepts a 1.71v to 1.89v supply voltage range. bypass each pin with a 0.1? capacitor to gnd. 24 outqn complementary q-dac output. negative terminal for current output. 25 outqp q-dac output. positive terminal for current output. 28 outin complementary i-dac output. negative terminal for current output. 29 outip i-dac output. positive terminal for current output. 35 av clk clock supply voltage. accepts a 3.135v to 3.465v supply voltage range. bypass with a 0.1? capacitor to gnd. 37 clkn complementary converter clock input. negative input terminal for differential converter clock. internally biased to av clk / 2. 38 clkp converter clock input. positive input terminal for differential converter clock. internally biased to av clk / 2. 39 torb two?-complement/binary select input. set torb to a cmos-logic-high level to indicate a two?- complement input format. set torb to a cmos-logic-low level to indicate a binary input format. torb has an internal pulldown resistor. 40 pd power-down input. set pd high to force the dac into power-down mode. set pd low for normal operation. pd has an internal pulldown resistor. 41 dori dual (parallel)/single (interleaved) port select input. set dori high to configure as a dual-port dac. set dori low to configure as a single interleaved-port dac. dori has an internal pulldown resistor.
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs _______________________________________________________________________________________ 9 detailed description architecture the max5873 high-performance, 12-bit, dual current- steering dac (figure 1) operates with dac update rates up to 200msps. the converter consists of input registers and a demultiplexer for single-port (interleaved) mode, followed by a current-steering array. during operation in interleaved mode, the input data registers demultiplex the single-port data bus. the current-steering array gen- erates differential full-scale currents in the 2ma to 20ma range. an internal current-switching network, in combina- tion with external 50 ? termination resistors, converts the differential output currents into dual differential output voltages with a 0.1v to 1v peak-to-peak output voltage range. an integrated 1.2v bandgap reference, control amplifier, and user-selectable external resistor determine the data converter? full-scale output range. reference architecture and operation the max5873 supports operation with the internal 1.2v bandgap reference or an external reference voltage source. refio serves as the input for an external, low- impedance reference source. refio also serves as a reference output when the dac operates in internal ref- erence mode. for stable operation with the internal ref- erence, decouple refio to gnd with a 1? capacitor. due to its limited output drive capability, buffer refio with an external amplifier when driving large external loads. the max5873? reference circuit (figure 2) employs a control amplifier to regulate the full-scale current i outfs for the differential current outputs of the dac. configured as a voltage-to-current amplifier, calculate the output current as follows: where i outfs is the full-scale output current of the dac. r set (located between fsadj and dacref) determines the amplifier? full-scale output current for the dac. see table 1 for a matrix of different i outfs and r set selections. i v r outfs refio set = ? ? ? ? ? ? ? 32 1 1 2 12 pin description (continued) pin name function 42 xor dac exclusive-or select input. set xor low to allow the data stream to pass unchanged to the dac input. set xor high to invert the input data into the dac. if unused, connect xor to gnd. 44 seliq dac select input. set seliq low to direct data into the q-dac inputs. set seliq high to direct data into the i-dac inputs. if unused, connect seliq to gnd. seliq? logic state is only valid in single-port (interleaved) mode. 45?6 b11, b10, b9, b8, b7, b6, b5, b4, b3, b2, b1, b0 data bits b11?0. in dual-port mode, data is directed to the i-dac. in single-port mode, the state of seliq determines where the data bits are directed. 61 dv dd1.8 digital supply voltage. accepts a supply voltage range of 1.71v to 1.89v. bypass with a 0.1? capacitor to gnd. 62?8 a11, a10, a9 a8, a7, a6, a5 data bits a11?5. in dual-port mode, data is directed to the q-dac. in single-port mode, data bits are not used. connect bits a11?5 to gnd in single-port mode. ep exposed pad. must be connected to gnd through a low-impedance path. table 1. i outfs and r set selection matrix based on a typical 1.200v reference voltage r set ( ? ) full-scale current i outfs (ma) calculated 1% eia std 2 19.2k 19.1k 5 7.68k 7.5k 10 3.84k 3.83k 15 2.56k 2.55k 20 1.92k 1.91k
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs 10 ______________________________________________________________________________________ analog outputs (outip, outin, outqp, outqn) each max5873 dac outputs two complementary cur- rents (outip/n, outqp/n) that operate in a single- ended or differential configuration. a load resistor converts these two output currents into complementary single-ended output voltages. a transformer or a differ- ential amplifier configuration converts the differential voltage existing between outip (outqp) and outin (outqn) to a single-ended voltage. if not using a transformer, the recommended termination from the output is a 25 ? termination resistor to ground and a 50 ? resistor between the outputs. to generate a single-ended output, select outip (or outqp) as the output and connect outin (or outqn) to gnd. sfdr degrades with single-ended operation. figure 3 displays a simplified diagram of the internal output structure of the max5873. clock inputs (clkp, clkn) the max5873 features flexible differential clock inputs (clkp, clkn) operating from a separate supply (av clk ) to achieve the lowest possible jitter perfor- mance. drive the differential clock inputs from a single- ended or a differential clock source. for single-ended operation, drive clkp with a logic source and bypass clkn to gnd with a 0.1? capacitor. clkp and clkn are internally biased to av clk / 2. this facilitates the ac-coupling of clock sources directly to the device without external resistors to define the dc level. the dynamic input resistance from clkp and clkn to ground is > 5k ? . data timing relationship figure 4 displays the timing relationship between digital cmos data, clock, and output signals. the max5873 features a 1.5ns hold, a -1.2ns setup, and a 1.1ns prop- agation delay time. a nine (eight)-clock-cycle latency exists between clkp/clkn, and outip/outin (outqp/outqn) when operating in single-port (inter- leaved) mode. in dual-port (parallel) mode, the clock latency is 5.5 clock cycles for both channels. latch xor/ decode latch cmos receiver latch latch dac outip outin latch xor/ decode latch latch dac outqp outqn fsadj torb seliq xor av clk clkn gnd clkp clk interface data11 data0 1.2v reference power-down block refio dacref pd gnd dv dd1.8 dv dd3.3 gnd av dd1.8 av dd3.3 dori max5873 figure 1. max5873 high-performance, 12-bit, dual current-steering dac
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs ______________________________________________________________________________________ 11 cmos-compatible digital inputs input data format select (torb, dori ) the torb input selects between two?-complement or binary digital input data. set torb to a cmos-logic- high level to indicate a two?-complement input format. set torb to a cmos-logic-low level to indicate a bina- ry input format. the dori input selects between a dual-port (parallel) or single-port (interleaved) dac. set dori high to configure the max5873 as a dual-port dac. set dori low to con- figure the max5873 as a single-port dac. in dual-port mode, connect seliq to ground. cmos dac inputs (a11/b11?0/b0, xor, seliq) the max5873 latches input data on the rising edge of the clock in a user-selectable two?-complement or bina- ry format. a logic-high voltage on torb selects two?- complement and a logic-low selects offset binary format. the max5873 includes a single-ended, cmos-compati- ble xor input. input data (all bits) are compared with the bit applied to xor through exclusive-or gates. pulling xor high inverts the input data. pulling xor low leaves the input data noninverted. by applying a previously encoded pseudo-random bit stream to the data input and applying decoding to xor, the digital input data can be decorrelated from the dac output, allowing for the trou- bleshooting of possible spurious or harmonic distortion degradation due to digital feedthrough on the printed circuit board (pcb). a11/b11?0/b0, xor, and seliq are latched on the ris- ing edge of the clock. in single-port mode ( dori pulled low) a logic-high signal on seliq directs the b11?0 data onto the i-dac inputs. a logic-low signal at seliq directs data to the q-dac inputs. in dual-port (parallel) mode ( dori pulled high), data on pins a11?0 are directed onto the q-dac inputs and b11?0 are directed onto the i-dac inputs. power-down operation (pd) the max5873 also features an active-high power-down mode that reduces the dac? digital current consumption from 21.5ma to less than 2? and the analog current consumption from 76ma to less than 2?. set pd high to power down the max5873. set pd low for normal operation. when powered down, the max5873 reduces the overall power consumption to less than 14w. the max5873 requires 10ms to wake up from power-down and enter a fully operational state. the pd integrated pulldown resistor activates the max5873 if pd is left floating. outip outin 1.2v reference current-source array dac refio fsadj r set i ref 10k ? dacref 1 f i ref = v refio / r set figure 2. reference architecture, internal reference configuration i out i out outin outip current sources current switches av dd figure 3. simplified analog output structure digital input code offset binary two? complement out_p out_n 0000 0000 0000 1000 0000 0000 0 i outfs 0111 1111 1111 0000 0000 0000 i outfs / 2 i outfs / 2 1111 1111 1111 0111 1111 1111 i outfs 0 table 2. dac output code table
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs 12 ______________________________________________________________________________________ applications information clk interface the max5873 features a flexible differential clock input (clkp, clkn) with a separate supply (av clk ) to achieve optimum jitter performance. use an ultra-low jitter clock to achieve the required noise density. clock jitter must be less than 0.5ps rms for meeting the speci- fied noise density. for that reason, the clkp/clkn input source must be designed carefully. the differen- tial clock (clkn and clkp) input can be driven from a single-ended or a differential clock source. differential clock drive is required to achieve the best dynamic performance from the dac. for single-ended opera- tion, drive clkp with a low noise source and bypass clkn to gnd with a 0.1? capacitor. figure 5 shows a convenient and quick way to apply a differential signal created from a single-ended source (e.g., hp/agilent 8644b signal generator) and a wide- band transformer. alternatively, these inputs can be dri- ven from a cmos-compatible clock source; however, it is recommended to use sinewave or ac-coupled differential ecl/pecl drive for best dynamic performance. t s t h t pd data11?ata0, xor clk dac output n - 1 n n + 1 n + 2 n - 5 n - 4 n - 3 n - 2 n - 6 seliq clk data in i0 q2 i2 q1 i1 i3 q3 q0 t s t h i out q out t pd i - 5 i - 4 i - 2 i - 3 i - 6 q - 6 q - 5 q - 4 q - 3 q - 2 (a) dual-port (parallel) timing diagram (b) single-port (interleaved) timing diagram figure 4. timing relationships between clock and input data for (a) dual-port (parallel) mode and (b) single-port (interleaved) mode
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs ______________________________________________________________________________________ 13 differential coupling using a wideband rf transformer use a pair of transformers (figure 6) or a differential amplifier configuration to convert the differential voltage existing between outip/outqp and outin/outqn to a single-ended voltage. optimize the dynamic perfor- mance by using a differential transformer-coupled out- put to limit the output power to < 0dbm full scale. pay close attention to the transformer core saturation char- acteristics when selecting a transformer for the max5873. transformer core saturation can introduce strong 2nd-order harmonic distortion especially at low output frequencies and high signal amplitudes. for best results, center tap the transformer to ground. when not using a transformer, terminate each dac output to ground with a 25 ? resistor. additionally, place a 50 ? resistor between the outputs (figure 7). for a single-ended unipolar output, select outip (outqp) as the output and ground outin (outqn) to gnd. driving the max5873 single-ended is not recom- mended since additional noise and distortion will be added. the distortion performance of the dac depends on the load impedance. the max5873 is optimized for 50 ? differential double termination. it can be used with a transformer output as shown in figure 6 or just one 25 ? resistor from each output to ground and one 50 ? resis- tor between the outputs (figure 7). this produces a full- scale output power of up to -2dbm, depending on the output current setting. higher termination impedance can be used at the cost of degraded distortion perfor- mance and increased output noise voltage. grounding, bypassing, and power- supply considerations grounding and power-supply decoupling can strongly influence the max5873 performance. unwanted digital crosstalk couples through the input, reference, power supply, and ground connections, and affects dynamic performance. high-speed, high-frequency applications require closely followed proper grounding and power- supply decoupling. these techniques reduce emi and internal crosstalk that can significantly affect the max5873 dynamic performance. use a multilayer pcb with separate ground and power- supply planes. run high-speed signals on lines directly above the ground plane. keep digital signals as far away from sensitive analog inputs and outputs, refer- ence input sense lines, common-mode input, and clock inputs as practical. use a symmetric design of clock input and the analog output lines to minimize 2nd-order harmonic distortion components, thus optimizing the dac? dynamic performance. keep digital signal paths short and run lengths matched to avoid propagation delay and data skew mismatches. wideband rf transformer performs single-ended-to- differential conversion single-ended clock source gnd 1:1 25 ? 25 ? clkp clkn to dac 0.1 f 0.1 f figure 5. differential clock-signal generation max5873 12 outip/outqp outin/outqn data11?ata0 wideband rf transformer t2 performs the differential-to-single-ended conversion t1, 1:1 t2, 1:1 gnd 50 ? 100 ? 50 ? v out , single-ended figure 6. differential-to-single-ended conversion using a wideband rf transformer
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs 14 ______________________________________________________________________________________ the max5873 requires five separate power-supply inputs for analog (av dd1.8 and av dd3.3 ), digital (dv dd1.8 and dv dd3.3 ), and clock (av clk ) circuitry. decouple each av dd , dv dd , and av clk input pin with a separate 0.1? capacitor as close to the device as possible with the shortest possible connection to the ground plane (figure 8). minimize the analog and digital load capacitances for optimized operation. decouple all three power-supply voltages at the point they enter the pcb with tantalum or electrolytic capacitors. ferrite beads with additional decoupling capacitors forming a pi-network could also improve performance. the analog and digital power-supply inputs av dd3.3 , av clk , and dv dd3.3 allow a 3.135v to 3.465v supply voltage range. the analog and digital power-supply inputs av dd1.8 and dv dd1.8 allow a 1.71v to 1.89v supply voltage range. the max5873 is packaged in a 68-pin qfn-ep pack- age, providing greater design flexibility, increased ther- mal efficiency, and optimized dac ac performance. the ep enables the use of necessary grounding tech- niques to ensure highest performance operation. thermal efficiency is not the key factor, since the max5873 features low-power operation. the exposed pad ensures a solid ground connection between the dac and the pcb? ground layer. the data converter die attaches to an ep lead frame with the back of this frame exposed at the package bottom surface, facing the pcb side of the package. this allows for a solid attachment of the package to the pcb with standard infrared reflow (ir) soldering techniques. a spe- cially created land pattern on the pcb, matching the size of the ep (6mm x 6mm), ensures the proper attachment and grounding of the dac. refer to the max5873 ev kit data sheet. designing vias into the land area and imple- menting large ground planes in the pcb design allow for the highest performance operation of the dac. use an array of at least 4 x 4 vias ( 0.3mm diameter per via hole and 1.2mm pitch between via holes) for this 68-pin qfn- ep package. connect the max5873 exposed paddle to gnd. vias connect the land pattern to internal or external copper planes. use as many vias as possible to the ground plane to minimize inductance. static performance parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from either a best straight-line fit (closest approximation to the actual transfer curve) or a line drawn between the end points of the transfer func- tion, once offset and gain errors have been nullified. for a dac, the deviations are measured at every indi- vidual step. differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step height and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees a monotonic transfer function. offset error the offset error is the difference between the ideal and the actual offset current. for a dac, the offset point is the average value at the output for the two midscale digital input codes with respect to the full scale of the dac. this error affects all codes by the same amount. max5873 12 outip/outqp outin/outqn data11?ata0 gnd 25 ? 50 ? 25 ? outp outn figure 7. differential output configuration max5873 12 outip/outqp outin/outqn data11?ata0 0.1 f av dd1.8 dv dd1.8 0.1 f 0.1 f 0.1 f av dd3.3 dv dd3.3 0.1 f av clk bypassing?ac level *bypass each power-supply pin individually. figure 8. recommended power-supply decoupling and bypassing circuitry
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs ______________________________________________________________________________________ 15 gain error a gain error is the difference between the ideal and the actual full-scale output voltage on the transfer curve, after nullifying the offset error. this error alters the slope of the transfer function and corresponds to the same percentage error in each step. dynamic performance parameter definitions signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital sam- ples, the theoretical maximum snr is the ratio of the full- scale analog output (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum can be derived from the dac? resolution (n bits): snr = 6.02 x n + 1.76 however, noise sources such as thermal noise, reference noise, clock jitter, etc., affect the ideal reading; therefore, snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first four harmonics, and the dc offset. noise spectral density the dac output noise floor is the sum of the quantiza- tion noise and the output amplifier noise (thermal and shot noise). noise spectral density is the noise power in 1hz bandwidth, specified in dbfs/hz. spurious-free dynamic range (sfdr) sfdr is the ratio of rms amplitude of the carrier frequen- cy (maximum signal components) to the rms value of their next-largest distortion component. sfdr is usually measured in dbc and with respect to the carrier frequen- cy amplitude or in dbfs with respect to the dac? full- scale range. depending on its test condition, sfdr is observed within a predefined window or to nyquist. two-tone intermodulation distortion (imd) the two-tone imd is the ratio expressed in dbc (or dbfs) of the worst 3rd-order (or higher) imd product(s) to either output tone. adjacent channel leakage power ratio (aclr) commonly used in combination with wideband code- division multiple-access (w-cdma), aclr reflects the leakage power ratio in db between the measured power within a channel relative to its adjacent channel. aclr provides a quantifiable method of determining out-of-band spectral energy and its influence on an adjacent channel when a bandwidth-limited rf signal passes through a nonlinear device. settling time the settling time is the amount of time required from the start of a transition until the dac output settles its new output value to within the converter? specified accuracy. glitch impulse a glitch is generated when a dac switches between two codes. the largest glitch is usually generated around the midscale transition, when the input pattern transitions from 011...111 to 100...000. the glitch impulse is found by integrating the voltage of the glitch at the midscale transition over time. the glitch impulse is usually specified in pv s.
max5873 12-bit, 200msps, high-dynamic-performance, dual dac with cmos inputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. 68l qfn.eps c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm c 1 2 21-0122 package outline, 68l qfn, 10x10x0.9 mm package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) revision history pages changed at rev 3: 1?6
e nglish ? ???? ? ??? ? ??? what's ne w p roducts solutions de sign ap p note s sup p ort buy comp any me mbe rs m axim > p roduc ts > h igh-speed data c onverters max5873 12-bit, 200msps, high-dynamic-performance, dual dac with c mos inputs quickview technical documents ordering info more information all ordering information notes: other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 1. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 2. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming c onventions . 3. * some packages have variations, listed on the drawing. "pkgc ode/variation" tells which variation the product uses. 4. devices: 1-4 of 4 m ax5873 fre e sam ple buy pack age : type pins footprint drawing code/var * te m p rohs/le ad-fre e ? m ate rials analys is max5873egk-d qfn;68 pin;100 mm dwg: 21-0122c (pdf) use pkgcode/variation: g6800-4 * -40c to +85c rohs/lead-free: no materials analysis max5873egk-td qfn;68 pin;100 mm dwg: 21-0122c (pdf) use pkgcode/variation: g6800-4 * -40c to +85c rohs/lead-free: no materials analysis max5873egk+d qfn;68 pin;100 mm dwg: 21-0122c (pdf) use pkgcode/variation: g6800+4 * -40c to +85c rohs/lead-free: lead free materials analysis max5873egk+td qfn;68 pin;100 mm dwg: 21-0122c (pdf) use pkgcode/variation: g6800+4 * -40c to +85c rohs/lead-free: lead free materials analysis didn't find what you need? next day product selection assistance from applications engineers parametric search applications help quickview technical documents ordering info more information des c ription key features a pplic ations /u s es key spec ific ations diagram data sheet a pplic ation n otes des ign guides e ngineering journals reliability reports software/m odels e valuation kits p ric e and a vailability samples buy o nline p ac kage i nformation lead-free i nformation related p roduc ts n otes and c omments e valuation kits doc ument ref.: 1 9 -3 4 4 6 ; rev 3 ; 2 0 0 7 -0 3 -0 7 t his page las t modified: 2 0 0 7 -0 3 -0 7 c ontac t us: send us an email c opyright 2 0 0 7 by m axim i ntegrated p roduc ts , dallas semic onduc tor ? legal n otic es ? p rivac y p olic y

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